SYNOPSYS: APPLICATION ENGINEER
Eligibility:
- BE / ME /MS with 0-1+ years of experience in logic design and implementation using FPGAs.
- Excellent communication and interpersonal skills, professional attitude and desire to succeed.
- Exposure to Xilinx synthesis software is a plus.
Scripting knowledge is desirable. - Understanding of Verification concepts and writing test benches
- Hands on Experience in Verilog and/or VHDL.
- Proven problem solving skills.
- Knowledge on Synthesis, back end flow, FPGA architecture and implementing designs in hardware.
Apply through the link here: CLICK HERE
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